Question 1

Time: 00:00:00
Which registers can interact with the secondary storage?

MAR

MAR

PC

PC

IR

IR

R0

R0

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Question 2

Time: 00:00:00
The internal Components of the processor are connected by _______ .

Processor intra-connectivity circuitry

Processor intra-connectivity circuitry

Processor bus

Processor bus

Memory bus

Memory bus

Rambus

Rambus

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Question 3

Time: 00:00:00
The registers,ALU and the interconnection between them are collectively called as _____ .

Process route

Process route

Information trail

Information trail

information path

information path

data path

data path

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Question 4

Time: 00:00:00
In memory-mapped I/O…

The I/O devices and the memory share the same address space

The I/O devices and the memory share the same address space

The I/O devices have a seperate address space

The I/O devices have a seperate address space

The memory and I/O devices have an associated address space

The memory and I/O devices have an associated address space

A part of the memory is specifically set aside for the I/O operation

A part of the memory is specifically set aside for the I/O operation

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Question 5

Time: 00:00:00
To overcome the lag in the operating speeds of the I/O device and the processor we use

Buffer spaces

Buffer spaces

Status flags

Status flags

Interrupt signals

Interrupt signals

Exceptions

Exceptions

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Question 6

Time: 00:00:00
The method of accessing the I/O devices by repeatedly checking the status flags is

Program-controlled I/O

Program-controlled I/O

Memory-mapped I/O

Memory-mapped I/O

I/O mapped

I/O mapped

None

None

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Question 7

Time: 00:00:00
The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is

Exceptions

Exceptions

Signal handling

Signal handling

Interrupts

Interrupts

DMA

DMA

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Question 8

Time: 00:00:00
The periods of time when the unit is idle is called as _____.

Stalls

Stalls

Bubbles

Bubbles

Hazards

Hazards

Both a and b

Both a and b

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Question 9

Time: 00:00:00
The time lost due to branch instruction is often referred to as _____.

Latency

Latency

Delay

Delay

Branch penalty

Branch penalty

None of the above

None of the above

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Question 10

Time: 00:00:00
The algorithm followed in most of the systems to perform out of order execution is ______.

Tomasulo algorithm

Tomasulo algorithm

Score carding

Score carding

Reader-writer algorithm

Reader-writer algorithm

None of the above

None of the above

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